USPTO Patents Application 10064424

10/01/04 FRI 11:33 FAX 886 2 23697233

JIANQ CHYUN IPO

@003

Customer No.; 31 561
AppUcation No.: 10/064,424
Docket No.; 9407-US-PA

AMENDMENT
Please amend the applicatioii as Indicated ticireafter.

In the Ciaims '

1. (original) A laminated substrate structure, wherein the structure
comprises a plurality of dielectric layers and a plurality of circuit layers stacked
with each other, each of the dielectric layetis has a plurality of via studs, and the
circuit layers are electrically coupled with each Other through the via studs, the
laminated substrate structure is characterized by a pattern of circuit layers
designed as landless.

2* (original) The laminated substrate structitre of claim 1, further
comprising at least a via opening layer, arranged orii the two most exterior dielectric
layers of the dielectric layers.

3. (original) The laminated substrate structure of claim 1, wherein the via
opening layer is a dielectric layer, and tliie dielectric layer has a plurality of
openings.

4. (original) The laminated substratie structure of claim 1, whether the via
opening layer is a solder mask layer, and tile soldier mask layer has: a plurality of
openings.

5. (original) A laminated substrate stirncture, comprising:

a plurality of dielectric layers, each of the dielectric layers has a plurality of
via studs; and

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10/01/04 FRI 11:34 FAX 886 2 23897203

JIANQ CHYUN IPO

@!004

Customer No.: ?1561
AppUcatiOD No»: 10/064,424
' Docket No.: 9407-trS-PA

a plurality of circuit layers, arranged in between the dielectric layers, the
circuit layers are electricaHy coupled to eaciti other throujg^h the via holes, wherein
the via holes In the two most exterior dielectric layers are used as a plurality of
solder pads directly*

6* (original) The laminated substrate structure of claim 5, wherein a pattern
of the circuit layers is designed as landless.

7. (origmal) The laminated substrate structure of claini 5, further
comprising at least a via opening layer, arramged on the two most exterior dielectric
layers of the dielectric layers*

8. (original) The laminated substratit structure of claim 7, wherein the via
opening layer is a dielectric layer, and tllie dielectric layer has a plurality of
openings.

9. (original) The laminated substrate structure of claim 7, whether the via
opening layer is a solder mask layer, and tile soldbr mask layer ha$ a plurality of
openings.

10. (canceled) A laminated substrate manufkcture method^ comprising:
providing a first supporter;

forming a patterned circuit on the first supporter;

forming a first dielectric layer on the first supporter, wherein the patterned
circuit is covered by the first dielectric layer to form a dielectric layer having the
patterned circuit on the first supporter;

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JIANQ CHYUN IPO

@005

Customer No.! 31561
Application No.: 10/064,424
Docket No.: 9407-US-PA

providing a second supporter;

forming a plurality of via studs on thtt seconid supporter;

forming a second dielectric layer on the second supporter, wherein the via
studs are extruded from the second dielectric layer !to form a dielectric layer having
the via studs on the second supporter; and

aligning and laminating a plurality o f dielectric layers having the patterned
circuit and a plurality of dielectric layers having the via studs, so that the via studs
penetrate through the first dielectric layer and electrically couple to the patterned
circuit

11. (canceled) The laminated substrate m^ufacture n^ethod of claim 10,
wherein after the dielectric layers having tllie patterned circuit and the dielectric
layers having the via holes are aligned and laminated, a curing sitep is further
performed, so that the first dielectric layer a-nd the second dielectric layer are cured
and the conductive positions are electrically coupled at the same time.

]2r (canceled) The laminated substriate manufacture method of claim 10,
wherein the metibod to form the patterned circuit comprises:

forming a conductive layer on the fintt suppiorter;

forming a patterned photoresist on tbie conductive layer; and

using the patterned photoresist as a mask, removing a portion of the

conductive layer that is not covered fay the patterned photoresist to form the

patterned circuit

PA(X S/ir RCVD AT 913112004 11:40:20 PM [Eastern Dayli^^

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JIANQ CHYUN IPO

@)006

Costomer No.: 31561
Application No.: 10/064,424
Docket No.: 9407-US-PA

13. (canceled) Tlie laminated substrate nnanufacture method of claim 10,
wherein the method to form the patterned circuit comprises:

forming a first conductive l^yer on the first isupporter;
forming a patterned photoresist o:ii the conductive layer, wherein the
patterned photoresist has a plurality of openings;

forming a second conductive layer in the second openings;
removing the patterned photoresist; and

removing the first condactive layeir that is not covered by the second
conductive layer to form the patterned circuiL

14. (canceled) The laminated substrate mdinufacture method of claim 10^
wherein the first dielectric layer is formed by using a coating method.

15. (canceled) The laminated substrate manufacture method of claim 10^
wherein the method to form the via studs coJmprises:

forming a conductive layer on the second suipporter;

forming a patterned photoresist on tliie conductive layer; and

using the patterned photoresist as a mask, removing a portion of the

conductive layer that is not covered by the patterned photoresist to form the via

studs.

16. (canceled) The laminated snbstrsate mannfiacture method of claim 10,
wherein the second dielectric layer is formedl by using a coating method.

17* (canceled) The laminated substrate manufacture method of claim 10,

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10/01/04 FRI 11:34 FAX 886 2 23697233

JIANQ CHYITN IPO

(21007

Customer No.: 31561
Application No.: 10/064,424
Docket No,: 9407-US-PA

lYherein tbe dielectric layers having the patterned circuit and the dielectric layers
having the via studs are laminated by using a vacuum thermal lamination method.

18* (canceled) A laminated substrate manofiftcture method, comprising:

forming a patterned circuit on a first supporter;

forming a first dielectric layer on the first supporter^ wherein the patterned
circuit is covered by the first dielectric layer to form a dielectric layer having the
patterned circuit on the first supporter;

forming a plurality of via studs on a siecond supporter;

forming a second dielectric layer on the second supporter, wherein the via
studs are extruded fVom the second dielectric layerito form a dielectric layer having
the via studs on the second supporter;

providing at least a via opening layer, wherein the via opening layer has a
plurality of openings; and

aligning and laminating a plurality of dielectric layers haviog the patterned
circuit, a plurality of dielectric layers having tbe via stud, and the via opening layer
so that the via studs penetrate through tbe first (dielectric layer and electrically
couple to the patterned circuit

19. (canceled) The laminated substrate manufacture method of claim 18,
wherein after the dielectric layers having the patteined circuit, tbe dielectric layers
having the via holes, and the via opening layer areialigned and laminated, a curing
step is further performed, so that the first dielectric layer and the second dielectric

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10/01/04 FRI 11:35 FAX 886 2 23697233

JIANQ CHYUN IPO

ilOOd

Customer No.: 31561
Application No.: 10/064^24
Docket No.: 9407-US-PA

layer are cured and tbe conductive positioiis are electrically coupled at the same
time*

20. (canceled) The laminated substrate mtoufacture method of claim 18»
wherein the method to form the patterned circuit comprises:

forming a conductive layer on the firsit suppiorter;

forming a patterned photoresist on tfale condhietive layer; and

using the patterned photoresist as a ma$k, removing a portion of the

conductive layer that is not covered by tlbe patterned photoresist to form the

patterned circuit.

21. (canceled) The laminated substrate manufacture method of claim 18^
wherein the method to form the patterned circuit comprises:

forming a first conductive layer on the first supporter;
forming a patterned photoresist on the ^conductive layer, wherein the
patterned photoresist has a plurality of openings;

forming a second conductive layer in the second openings;
removing the patterned photoresist; imd

removing the first conductive layer that. is not covered by the second
conductive layer to form the patterned circuit.

22. (canceled) The laminated substrate manufacture method of claim 18,
wherein the first dielectric layer is formed by using a coating method.

23. (canceled) The laminated substrate manufacture method of claim 18,

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10/01/04 FRI 11:35 FAX 886 2 23697233

JIANQ CHYUN IPO

121009

Customer No.: 31561
Application No.: 10/064,424
Docket No.: 9407-US^PA

wherein the method to form the via studs comprises:

forming a conductive iayer on the second supporter;

forming a patterned photoresist on thte condkictive layer; and

using the patterned photoresist as a maSiCy removing a portion of the

conductive layer that is not covered by the patterned photoresist to form the via

studs.

24* (canceled) The laminated substrate manufacture method of claim 18,
wherein the second dielectric layer is formed; by usjng a coating method.

25. (canceled) The laminated substrate manufacture method of claim 18^
wherein the dielectric layers having the patterned circuit, the dielectric layers
having the via studs, and the via opening layer arte laminated by using a vacuum
thermal lamination method.

26. (canceled) The laminated substrate manufacture method of claim 18,
wherein the methods to form the openings comprise mechanical drilling, laser
drilling, and punch.

27. (canceled)A laminated substrate manufacturiog process, comprising
steps of:

forming a plurality of patterned circmit parts;
forming a plurality of via stud parts;
forming a plurality of via opening pa:rts; and

laminating the patterned circuit partsi, the vis stnd parts amd the via opening

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10/01/04 FRI 11:35 FAX 886 2 23697233

JIANQ CHYUN IPO

121010

parts to complete tlie laminated substrate.

Customer No.: 31561
ApplicatioD No.: 10/064,424
Docket No.: 9407.US-PA

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